THE RESEARCH ARCHIVE
Experiments, reports, and ideas from the Loom and Welvet journey. A record of what was being explored, measured, and reconsidered.
Can you train complex nets on constrained consumer edge hardware without running out of memory or locking up live inference? All sweeps here ran natively on a Raspberry Pi 3B (1 GB RAM): 29 train modes × 34 dtypes × 20 quants. SGD is a baseline, not a winner — TweenSplit families lead Lucy Score (Throughput × Availability × Acc) by keeping serve+train alive under tight VRAM.
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Lucy serve+train sprints of every Welvet layer, each on its own tide dashboard, with a master ocean view that crowns the best train mode and dtype. Cheap one-epoch scan across 34 dtypes, 23 modes, and single/bicameral/tricameral — including the MHA finding that 1-bit recipes beat 32-bit giants.
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Welvet adaptive framework: sine adaptation under switching targets — SoftAcc, duty-cycle Availability, and MobileScore across dtype × quant × train mode × architecture on SIMD. Which cells keep serving answers while they learn, and what that costs in RAM.
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Architectural exploration of 3D wafer stacking & hardware spatial layout: mapping Welvet's 3D volumetric XYZ step mesh directly to vertical wafer-to-wafer DRAM vaults, eliminating CGO FFI delays with Plan 9 assembly, and enforcing storage truth across 34 dtypes and sub-byte quants.
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Welvet numeric demotion: when downcasting dtypes and shrinking models fails to buy wall-clock speed, and what the polymorphic numeric path actually costs on real hardware. Same Dense net across dtype, packed quant, and full weight×activation perm — measured size vs train time.
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Weight-agnostic compression: dense matrices collapse to 64-bit layer seeds, with non-differentiable evolutionary search. Edge checkpoints measured in bytes, not megabytes.
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Experimental acceleration: Plan 9 SIMD on ARM and x86 (no CGO or CUDA), Apple Metal zero-copy, and Qualcomm Hexagon NPU offload with the Drift Spectrum.
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Live ingestion from PyTorch, TensorFlow, JAX, and scikit-learn into portable .entity checkpoints, plus a three-way runtime compare against ONNX Runtime, LiteRT, and Core ML.
Per-layer NPU offload via OpenVINO, the small-tensor latency tax, 28x INT8 wins on large ops, and honest notes on when deterministic hardware still drifts from software.
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Why Plan 9 assembly wins on fat matrices but inverts on volumetric grids, the WebGPU validation tax, and the pivot to load-time GPU graph compilation.
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ENTITY native checkpoints, the Planet Bridging hub, and pure Go plus WebGPU: why importing a model is not the same as shipping a portable brain.
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The flagship M-POLY-VTD deep dive: volumetric dispatch, 21 numeric types, target propagation, and side-by-side Go ML comparisons.
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How Loom's operation mesh and release trajectory tightened the local-AI deployment story on consumer hardware.
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Cache-aware tiling: why Apple Silicon plus Loom can outrun big discrete GPUs on the right workloads.
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